CALL FOR PAPERS
- The aim of the VLSI Design & Test Symposium (VDAT-2024) is to foster a platform where academia, researchers, startups, and industrial practitioners can exchange innovative ideas, share experiences, and disseminate knowledge across diverse realms of VLSI Design and Testing.
We invite submissions of abstracts for papers and accompanying presentations that delve into highly technical content and explore emerging trends across VLSI Design and Testing domains. To submit your work, kindly provide an electronic copy of the entire paper, formatted according to the IEEE double-column specifications, limited to a maximum of 6 pages and A4 size. Submissions are welcome in, but not limited to, the following areas:
TRACKS
Emerging Devices and Material Technologies
Emerging Devices and Modeling- Si-Photonics and Optoelectronics devices
- MEMS/NEMS
- Organic electronics
- 2D and advanced material electronics
- Emerging memory technologies
VLSI Circuit and System Design
- Analog, Mixed Signal and RF IC Design
- Digital VLSI Architectures
- Clock-generation and distribution circuits including all digital PLLs and DLLs
- Circuit design for reliability effects such as gate oxide integrity, electro-migration, ESD, HCI, NBTI, PBTI etc.
- Hardware accelerators for machine learning (ML) and deep learning algorithms
- Hardware implementations of ML algorithms for applications like image/object recognition, computer vision, speech recognition, and natural language processing
- ML-based intelligence in IoT under highly constrained energy/power requirements
- Secure and intelligent system on chip (SoC) design for automotive, health and defense applications
CAD for VLSI
- Logic and behavioral synthesis
- Floor planning, Placement, Clock Tree Synthesis and Routing algorithms
- Design Automation and Methodologies
- Trusted design automation and Tool flow
Testing and Verification
- Design verification, Test, Reliability and Fault tolerance
- Formal verification
- DFT
- Fault modeling
- Pre Silicon Design, Verification and Validation
- Post-silicon validation
- Analog - Mixed-Signal - RF Test
- Functional safety and test methods
- Testing memories and regular logic arrays
- Design for manufacturability and yield analysis.
Embedded Systems Design
- FPGA based designs, Hardware/Software co-design and verification
- Audio, Image and video processing
- Reconfigurable systems
- Microcontroller, ARM, IoT and FPGA-based embedded systems design
- Embedded software
- CAD for embedded systems
- CAD for FPGA and embedded systems
Emerging Processors for System Design
- RISC-V based Design
- Artificial intelligence and ML-based systems, Cyber-Physical Systems
- Cryptographic Architectures
- Neuromorphic Architectures
- Quantum Computing
Submission Guidelines
- Authors are invited to submit original, unpublished research manuscripts on the above topics. Papers should be submitted in pdf format (Portable Document Format) as per the IEEE Conference paper format.
- The number of pages should not exceed six A4 size pages and paper should be uploaded through Microsoft CMT.
- There will be double blind review of the paper. Therefore, do not include 'authors' name in submitted paper. A paper with 'authors' names will not be considered for review.
- The paper must include an abstract of about 250 words with maximum of five keywords.
- Authors of the accepted papers will be informed by email. Information about necessary revisions will be communicated to the corresponding author through email.
- The author(s) will have to incorporate the suggestions and will have to send the revised camera-ready copy of the paper as per the final submission guidelines within the given time limit.
- It is mandatory for at least one of the authors to register for publication of the paper in proceedings. For the author presenting more than one papers, it is mandatory to register and present each paper separately.
